This category is for minimal processors: CPUs that use various design strategies to strongly minimize the component count needed to do work; to be as simple as possible. This includes: MISC (Minimal Instruction Set Computers), SISC (Simple Instruction Set Computers), ROSC (Removed Operand Set Computer), ZISC (Zero Instruction Set Computers), Forth and stack processors, and other methods. This was one of the original goals of RISC (Reduced Instruction Set Computers), but many newer RISC processors are more complex than the original CISC (Complex Instruction Set Computers) processors they challenged, and some current CISC processors are astonishingly complex. Minimal processors will be very useful in, and may become important for, mobile and ubiquitous computing.
Related categories 4
E25 Computer Architecture: Lab 5: OISC: One Instruction Set Computer
Class project to design and implement One Instruction Set Computer; using instruction: SUBLEQ A B C. Meaning: subtract value in M(A) from M(B) and store it in M(B), if result is not positive, go to instruction C. Descriptions, diagrams, code, tables.
References, links to Forth and stack machines in various technologies.
Java Optimized Processor
JOP is the implementation of a small java processor with the JVM fitting in a FPGA.
Microprocessor Architectures from VLIW to TTA
By Henk Corporaal; John Wiley, 1998, ISBN 047197157X. Introduces Transport Triggered Architectures, TTAs. In standard architectures, programmed operations trigger internal data transports. TTAs work by programming data transports themselves. This removes bottlenecks, allows for new code generation optimizations, uses hardware more efficiently.
Minimal Instruction Set Computers
Stack-based processors, 5-bit words, 25 instructions, 7000 transistors, 80 MIPS, 50 milliwatts, low cost; designed by Chuck Moore, creator of Forth programming language.
Minimal instruction set, small, low power 16-bit CPU optimized to run Forth on a Xilinx FPGA. When system is stable, VHDL source code for CPU and all other code will be released to make a full open source public domain CPU.
A No Instruction Set Processor
Benefits: simple, easily pipelined, useful in self-clocked systems, very flexible and optimizable, good memory access, highly. Problems: awkward to program. [cowlark.com]
PTSC: Patriot Scientific Corp.
Makes IGNITE I ROSC (Removed Operand Set Computer), PSC1000 32-bit embedded shBoom-based microprocessor line, many ISDN interface products, sophisticated antenna/radar technologies.
Course on minimal processors: Guided Exploration of two FPGA-based CPU Designs, led by John Rible.
Stack Computers & Forth
Philip J. Koopman, Jr., CMU page. Reports, studies, and links. Compares: CISC, RISC, Stack systems; 2 and 3 stack systems.
Stack Computers: The New Wave
By Philip J. Koopman, Jr; Ellis Horwood, 1989, ISBN 0470214678. Read on-line, or download in formats: HTML, PDF, zip file. First book to explore a new breed of stack computers led by introduction of Novix NC4016. [Free]
Simple one instruction language; type of OISC; specifications from Clive Gifford eigenratios self-interpreter page. Each subleq instruction has 3 operands which are memory addresses. Oleg Mazonka.
Embedded systems consultant for small (8/16-bit) and distributed microprocessor systems. Contract hardware and software development for most microcontrollers. Specialist: Forth, Assembly, C. By Bradford J. Rodriguez, Ph.D.
Triangle Digital Services Ltd.
Small, powerful Forth embedded computers: let you quickly design applications: controls, portable instruments, terminals, data loggers, GPS, CAN bus, multitasking, LCD and keyboard systems. High level language makes development simple and fast; needs no PROM programmer. Forth hardware and software.
The Ultimate RISC
Explains extreme, simple RISC, with only one instruction, move memory to memory; yet it is useful. Revision of paper first published in ACM Computer Architecture News.
Wikipedia: One Instruction Set Computer
Online encyclopedia article about this single machine language opcode, with links to related articles.
Wikipedia: Transport Triggered Architectures
Online encyclopedia article about this approach to computer architecture.
Last update:May 30, 2014 at 5:45:09 UTC