The DLX is a reduced instruction set computer (RISC) processor architecture. It is mainly a cleaner, simpler MIPS architecture, with a simple 32-bit load/store design, and intended mainly for education, as are Donald Knuth's MIX and MMIX architectures. All three are widely used in college-level computer architecture courses. DLX was introduced in the textbook "Computer Architecture: A Quantitative Approach", by John L. Hennessy and David A. Patterson, the main designers of the MIPS and Berkeley RISC designs, respectively, which are the two benchmark RISC designs.
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The DLX Instruction Set Architecture Handbook
By Philip M. Sailer, David R. Kaeli; Morgan Kaufmann, 1996, ISBN 1558603719, 1st edition. Definitive work on DLX instructions. Information and abstract. ACM Portal.
ASynchronous, open source, Processor IP of the DLX Architecture. Goal: show feasibility to design and deliver asynchronous open IPs in portable, re-usable way. Information, downloads. Open source hardware.
David R. Kaeli, Professor
Director of Northeastern University Computer Architecture Research Laboratory, and co-author of Computer Architecture: A Quantitative Approach. Professional information with some links.
Documents: getting started, instruction set summary and description, simulator manual.
DLX Instruction Slides
Tables of instructions, categorized, as PDF slides. By Guy Even, Tel Aviv University. [PDF]
The DLX Processor
Class overview with tables (instruction format, set) and diagrams (timing), some other information. By Ethan Miller, University of Maryland.
Implementation of 5-stage DLX Pipeline
Introductory tutorial with definitions, explanations, examples to show basic pipelining ideas; applet simulation lets users choose instructions to run, and see how pipeline works from direct experience.
Introduction to Operating Systems
DLXOS information needed for programming, from introductory course on OSs.
Norman Matloff's DLX Tutorial
Information on DLX processor simulator and compiler, DLXsim, interactive program, loads assembly programs and simulates operation of computer on them, single-stepping or continuous execution.
Out of Order Execution
Master's Thesis: Design and Evaluation of a RISC Processor with a Tomasulo Scheduler. Uses DLX. HTML, PS, GZ, PDF.
Superscalar DLX Processor
Diagram, description, download.
Encyclopedia article with links to many related topics.
Last update:February 9, 2015 at 8:15:09 UTC