About Real Intent
Breakthrough in logic verification. Funded by very experienced people from EDA
The Spyglass suite of tools uses predictive analysis technique that performs structural analysis on Verilog and VHDL RTL to detect design problems in SoCs and ASICs.
CoreEL Technologies Pvt. Ltd
Offers design services in the area of FPGA design, Embedded Design, PCB Design and ASIC design.
Forte Design Systems
Develops software which aids your ASIC flow from design through verification.
Icarus Verilog Interactive
An Open Source interactive simulator frontend for Verilog and VHDL circuit simulation.
Developers of innovative design verification and coverage software.
Last update:November 1, 2014 at 16:05:03 UTC